`timescale 1ns / 1ps

module SRLatch_sim;
    reg S,R;
    wire Q,Q_;
    SRLatch exa(R,S,Q,Q_);
    initial begin
            S=1;R=0;
            #5; S=0;R=0;
            #5; S=0;R=1;
            #5 ;S=1;R=1;   
    end
endmodule
